D Flip-Flop

D-FLIP-FlOP

The D (data) flip flop is a slight modification of the SR flip flop . An SR flip flop is converted to a D flip flop by inserting an Inverter between S and R and assigning the symbol D to the single input. The D input is sampled during the occurrence of a clock transition from 0 to 1. If D=1, the output of the flip flop goes to the 0 state.

Block Diagram of D flip flop :

                              

click here for J-K flip flop

Characteristic of D-Flip-flop:

                       

          From the characterstic table of the D flip flop are Q is determined by D input. Q output of the flip flop receive its value from the D input every time that the clock signal goes through a transition from 0 to 1.

Circuit Diagram of D flip flop :

J-K flip flop